(VRV32M Multiplication Operations
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I7
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I6
sVwid_order
p12
I6
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_MUL
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP000_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F000_S000_I000
p34
sVdescription
p35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 7.1
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p40
sVcoverage_loc
p41
Visacov.rv32m_mul_cg.cp_rs1\u000aisacov.rv32m_mul_cg.cp_rs2\u000aisacov.rv32m_mul_cg.cp_rd\u000aisacov.rv32m_mul_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mul_cg.cp_rd_rs2_hazard
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F000_S000_I001
p63
sg35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p64
sg37
VUnprivileged ISA\u000aChapter 7.1
p65
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p66
sg41
Visacov.rv32m_mul_cg.cp_rs1_value\u000aisacov.rv32m_mul_cg.cp_rs2_value\u000aisacov.rv32m_mul_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mul_cg.cp_rs1_toggle \u000aisacov.rv32m_mul_cg.cp_rs2_toggle
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
a(V002
p73
g1
(g29
g3
Ntp74
Rp75
(dp76
g8
V002
p77
sg23
VVP_ISA_F000_S000_I002
p78
sg35
Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored.
p79
sg37
VUnprivileged ISA\u000aChapter 7.1
p80
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p81
sg41
Visacov.rv32m_mul_cg.cp_rd_value\u000aisacov.rv32m_mul_cg.cp_rd_toggle
p82
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp83
sg15
(lp84
sg53
(lp85
sg13
(dp86
g56
I0
ssbtp87
asVrfu_list_1
p88
(lp89
sg53
(lp90
sg13
(dp91
sbtp92
a(V001_MULH
p93
g1
(g18
g3
Ntp94
Rp95
(dp96
g22
I3
sg8
g93
sg23
VVP_IP000_P001
p97
sg25
(dp98
sg12
I1
sg15
(lp99
(V000
p100
g1
(g29
g3
Ntp101
Rp102
(dp103
g8
V000
p104
sg23
VVP_ISA_F000_S001_I000
p105
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p106
sg37
VUnprivileged ISA\u000aChapter 7.1
p107
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p108
sg41
Visacov.rv32m_mulh_cg.cp_rs1\u000aisacov.rv32m_mulh_cg.cp_rs2\u000aisacov.rv32m_mulh_cg.cp_rd\u000aisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulh_cg.cp_rd_rs2_hazard
p109
sg43
I3
sg44
I3
sg45
I1
sg46
I32
sg47
g48
sg49
g48
sg50
(lp110
sg15
(lp111
sg53
(lp112
sg13
(dp113
g56
I0
ssbtp114
a(V001
p115
g1
(g29
g3
Ntp116
Rp117
(dp118
g8
V001
p119
sg23
VVP_ISA_F000_S001_I001
p120
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p121
sg37
VUnprivileged ISA\u000aChapter 7.1
p122
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p123
sg41
Visacov.rv32m_mulh_cg.cp_rs1_value\u000aisacov.rv32m_mulh_cg.cp_rs2_value\u000aisacov.rv32m_mulh_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulh_cg.cp_rs1_toggle \u000aisacov.rv32m_mulh_cg.cp_rs2_toggle
p124
sg43
I3
sg44
I3
sg45
I1
sg46
I32
sg47
g48
sg49
g48
sg50
(lp125
sg15
(lp126
sg53
(lp127
sg13
(dp128
g56
I0
ssbtp129
a(V002
p130
g1
(g29
g3
Ntp131
Rp132
(dp133
g8
V002
p134
sg23
VVP_ISA_F000_S001_I002
p135
sg35
Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers
p136
sg37
VUnprivileged ISA\u000aChapter 7.1
p137
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p138
sg41
Visacov.rv32m_mulh_cg.cp_rd_value\u000aisacov.rv32m_mulh_cg.cp_rd_toggle
p139
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp140
sg15
(lp141
sg53
(lp142
sg13
(dp143
g56
I0
ssbtp144
asg88
(lp145
sg53
(lp146
sg13
(dp147
sbtp148
a(V002_MULHU
p149
g1
(g18
g3
Ntp150
Rp151
(dp152
g22
I3
sg8
g149
sg23
VVP_IP000_P002
p153
sg25
(dp154
sg12
I2
sg15
(lp155
(V000
p156
g1
(g29
g3
Ntp157
Rp158
(dp159
g8
V000
p160
sg23
VVP_ISA_F000_S002_I000
p161
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p162
sg37
VUnprivileged ISA\u000aChapter 7.1
p163
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p164
sg41
Visacov.rv32m_mulhu_cg.cp_rs1\u000aisacov.rv32m_mulhu_cg.cp_rs2\u000aisacov.rv32m_mulhu_cg.cp_rd\u000aisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard
p165
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp166
sg15
(lp167
sg53
(lp168
sg13
(dp169
g56
I0
ssbtp170
a(V001
p171
g1
(g29
g3
Ntp172
Rp173
(dp174
g8
V001
p175
sg23
VVP_ISA_F000_S002_I001
p176
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p177
sg37
VUnprivileged ISA\u000aChapter 7.1
p178
sg39
VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p179
sg41
Visacov.rv32m_mulhu_cg.cp_rs1_value\u000aisacov.rv32m_mulhu_cg.cp_rs2_value\u000aisacov.rv32m_mulhu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhu_cg.cp_rs2_toggle
p180
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp181
sg15
(lp182
sg53
(lp183
sg13
(dp184
g56
I0
ssbtp185
a(V002
p186
g1
(g29
g3
Ntp187
Rp188
(dp189
g8
V002
p190
sg23
VVP_ISA_F000_S002_I002
p191
sg35
Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers
p192
sg37
VUnprivileged ISA\u000aChapter 7.1
p193
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p194
sg41
Visacov.rv32m_mulhu_cg.cp_rd_value\u000aisacov.rv32m_mulhu_cg.cp_rd_toggle
p195
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp196
sg15
(lp197
sg53
(lp198
sg13
(dp199
g56
I0
ssbtp200
asg88
(lp201
sg53
(lp202
sg13
(dp203
sbtp204
a(V003_MULHSU
p205
g1
(g18
g3
Ntp206
Rp207
(dp208
g22
I3
sg8
g205
sg23
VVP_IP000_P003
p209
sg25
(dp210
sg12
I3
sg15
(lp211
(V000
p212
g1
(g29
g3
Ntp213
Rp214
(dp215
g8
V000
p216
sg23
VVP_ISA_F000_S003_I000
p217
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p218
sg37
VUnprivileged ISA\u000aChapter 7.1
p219
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p220
sg41
Visacov.rv32m_mulhsu_cg.cp_rs1\u000aisacov.rv32m_mulhsu_cg.cp_rs2\u000aisacov.rv32m_mulhsu_cg.cp_rd\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard
p221
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp222
sg15
(lp223
sg53
(lp224
sg13
(dp225
g56
I0
ssbtp226
a(V001
p227
g1
(g29
g3
Ntp228
Rp229
(dp230
g8
V001
p231
sg23
VVP_ISA_F000_S003_I001
p232
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p233
sg37
VUnprivileged ISA\u000aChapter 7.1
p234
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p235
sg41
Visacov.rv32m_mulhsu_cg.cp_rs1_value\u000aisacov.rv32m_mulhsu_cg.cp_rs2_value\u000aisacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhsu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhsu_cg.cp_rs2_toggle
p236
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp237
sg15
(lp238
sg53
(lp239
sg13
(dp240
g56
I0
ssbtp241
a(V002
p242
g1
(g29
g3
Ntp243
Rp244
(dp245
g8
V002
p246
sg23
VVP_ISA_F000_S003_I002
p247
sg35
Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number
p248
sg37
VUnprivileged ISA\u000aChapter 7.1
p249
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p250
sg41
Visacov.rv32m_mulhsu_cg.cp_rd_value\u000aisacov.rv32m_mulhsu_cg.cp_rd_toggle
p251
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp252
sg15
(lp253
sg53
(lp254
sg13
(dp255
g56
I0
ssbtp256
asg88
(lp257
sg53
(lp258
sg13
(dp259
sbtp260
asVrfu_list_0
p261
(lp262
sg88
(lp263
sVvptool_gitrev
p264
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p265
sVio_fmt_gitrev
p266
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p267
sVconfig_gitrev
p268
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p269
sVymlcfg_gitrev
p270
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p271
sbtp272
.